Over recent years, as the miniaturization of semiconductor devices has progressed, the planar region occupied by semiconductor elements has become smaller, and regions in which transistors are formed (active regions) have become smaller. In a planar transistor, as the size of the active region decreases, the channel length or the channel width decreases, giving rise to problems such as a short channel effect.
Accordingly, patent literature articles 1 and 2 (Japanese Patent Kokai 2008-311641 and Japanese Patent Kokai 2009-10366) propose semiconductor devices in which, instead of a planar transistor, a vertical transistor in which the channel length and the channel width can be maintained even in a miniaturized region is provided.
In a vertical transistor, unlike in a planar transistor, a semiconductor pillar is formed in a vertical direction on the main surface of a semiconductor substrate, and when the transistor is on, a channel is formed in the semiconductor pillar in a direction perpendicular to said main surface. Therefore vertical transistors can be applied more effectively than planar transistors in semiconductor memory elements, typified by miniaturized DRAMs.
As an application example of a semiconductor device provided with such a vertical transistor, patent literature article 3 (Japanese Patent Kokai 2012-74684) discloses a vertical transistor in which trenches 8a are formed from a plurality of semiconductor pillars 1ba and the main surface of a semiconductor substrate 1, and gate electrodes 8 (word lines W) are provided on the side surfaces of the semiconductor pillars 1ba forming the inside surfaces of the trenches 8a (FIG. 1B). Thus, by providing two gate electrodes 8 in one trench 8a, a semiconductor device supporting miniaturization can be achieved.